Trapped ion technology for next generation quantum computers

Scanning electron micrograph of the HOA-2 trap designed and fabricated at Sandia National Laboratories. Figure adapted with permission from [18]. A single trap houses all the ions. Control electrodes are used to load, remove and move ions. This architecture does not scale beyond 50-100 qubits because of gate implementation challenges in long ion chains.

Researchers at Princeton University and Duke University collaborated to develop methods to design the next generation of quantum computers.

Their study focused on QC systems built using Trapped-Ions (TI) technology, which is one of the current front-running QC hardware technologies. By bringing together computer architecture techniques and device simulations, the team showed that co-designing near-term hardware with applications can potentially improve the reliability of TI systems by up to four orders of magnitude.

In a TI system, atomic ion qubits (like a Calcium or Ytterbium ion) are isolated and trapped in an electric field.

Companies such as IonQ, Honeywell, and Alpine Quantum Technologies, as well as academic groups like ours at Duke University, are working to build QC systems using such hardware. Published results on single ion chains include the complete control of 11 qubits at IonQ and quantum simulations on 53 qubits at the University of Maryland.

While current TI devices have shown significant promise, larger devices with 50 to 100 qubits are necessary to demonstrate advantages over classical computing. However, most current TI devices have a fundamental scaling bottleneck—they are based on a monolithic single-trap architecture, where all ions are housed in the same trapping zone. In this architecture, qubit control and gate implementation become increasingly challenging as more ions are added to the trap.

Recognizing these difficulties, an alternative scalable architecture, called Quantum Charged Coupled Device (QCCD) was proposed as early as 2002. A QCCD system is composed of a set of traps, each holding a small number of ions, instead of a single large trap. To build the next generation of QCCD systems with 50 to 100 qubits, hardware designers have to tackle a variety of conflicting design choices.

To study these design choices efficiently, the researchers built a design tool flow which estimates the reliability, execution time and other metrics for a set of quantum programs on a specified QCCD device. This tool flow consists of two parts. The first part is a compiler which maps the program down to the primitive operations that will be available on QCCD systems. The second part is a QCCD simulator which uses realistic performance and noise models for QCCD systems, derived from hardware characterization works, to estimate the quality of an application execution.

Using this tool flow, they identified a sweet spot of 15 to 25 ions per trap that will likely work well across applications, providing the best tradeoff between gate errors at high trap sizes and shuttling errors at low trap sizes. (

The paper can be read there.

Read more.